Name
Title | ||
|---|---|---|
Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic |
Abstract | ||
|---|---|---|
This paper presents a new architecture for distributed arithmetic (DA) based Least Mean Square (LMS) adaptive filter with low hardware complexity and critical path. It is well known that for DA based adaptive filter, the throughput depends on critical path and number of clock cycles to produce the output. In the proposed technique, we maintained the same number of clock cycles using multiplexed look-up tables (LUTs) which reduces the hardware complexity and critical path compared to best existing scheme. For instance, the hardware complexity can be lowered down by α.N, whereas the critical path can be reduced by TA + TM, with α, N, TA and TM being the number of reduced hardware elements, number of filter taps, adder and multiplexer computational delays, respectively. Synthesis result shows that for almost similar area and power performance, the proposed scheme achieves a gain of 27.6% due to clock speedup which results in more throughput and power can be lowered compared to best existing scheme. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/VLSID.2017.16 | 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
Adaptive filter (ADF),distributed arithmetic (DA),least mean square (LMS),offset binary coding (OBC) | Least mean squares filter,Adder,Computer science,Real-time computing,Electronic engineering,Multiplexer,Adaptive filter,Critical path method,Throughput,Multiplexing,Speedup | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-5090-5741-2 | 1 |
PageRank | References | Authors |
0.37 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohd Tasleem Khan | 1 | 10 | 4.69 |
| Shaik Rafi Ahamed | 2 | 14 | 8.82 |
| Forrest Brewer | 3 | 414 | 62.95 |