Name
Abstract | ||
|---|---|---|
This paper presents a fully integrated on-chip III-V HEMT and CMOS hybrid technology, implementing a 6b 125MSps successive approximation register (SAR) ADC. On-chip integration is achieved by using a hybrid PDK that permits direct integration of Au-free III-V devices into a foundry-proven CMOS process. The prototype utilizes an on-chip integrated InGaAs sampling switch and remaining circuits in CMOS. A “more than Moore” design and fabrication methodology has been adopted to overcome CMOS performance limitation. On-chip InGaAs switch integration results in reduction of parasitic elements, enhance the settling speed and superior dynamic performance. In this work the ADC consumes 1.99mW from a 1.8V supply achieving 33.7dB SNDR at nyquist and occupies 0.0225mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISICIR.2016.7829734 | 2016 International Symposium on Integrated Circuits (ISIC) |
Keywords | DocType | ISSN |
HEMT,III–V,on-chip,integrated,CMOS,SAR,ADC,low power,InGaAs,constant common mode,Hybrid,PDK | Conference | 2325-0631 |
ISBN | Citations | PageRank |
978-1-4673-9020-0 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sunny Sharma | 1 | 0 | 0.34 |
| Siau Ben Chiah | 2 | 0 | 1.69 |
| Xing Zhou | 3 | 12 | 9.90 |
| Chirn Chye Boon | 4 | 136 | 26.81 |