Name
Abstract | ||
|---|---|---|
This work discusses design considerations for implementing widely tunable delay cells with good matching properties, low jitter, and robust communication to adjacent circuits. Previously unreported effects that result in signal-dependent delay are discussed and eliminated. A 1.2 V 65 nm CMOS prototype achieves a tunability range from 5 ns to 10 μs, with a matching standard deviation of 2.3% and a jitter standard deviation of 0.065%. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/CICC.2017.7993651 | 2017 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | Field | DocType |
Digital delay circuits | Computer science,Delay,Electronic engineering,CMOS,Jitter,Low jitter,Electronic circuit,Standard deviation | Conference |
ISBN | Citations | PageRank |
978-1-5090-5192-2 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu Chen | 1 | 391 | 75.79 |
| Rajit Manohar | 2 | 1038 | 96.72 |
| Yannis P. Tsividis | 3 | 333 | 73.63 |