Paper Info
Title
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.
Abstract
Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (f s u003e100MS/s) and high-resolution (ENOBu003e9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoMu003c20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.
Year
Venue
Field
2017
ISSCC
Electrical efficiency,Capacitor,Computer science,CMOS,Electronic engineering,Effective number of bits,Successive approximation ADC,Transistor,Electrical engineering,Operational amplifier,Amplifier
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
4
9
Name
Order
Citations
PageRank
Kentaro Yoshioka100.34
Tomohiko Sugimoto2122.03
Naoya Waki321.09
SinNyoung Kim422.35
Daisuke Kurose5175.11
Hirotomo Ishii672.03
Masanori Furuta7223.56
Akihide Sai8208.25
Tetsuro Itakura918733.44