Paper Info
Title
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
Abstract
To benefit from Mooreu0027s law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are required, increasing system cost and form-factor. Traditional radio architectures require extensive use of high-quality passives, which might use large silicon area or not be available due to process limitations. Fast time to market also demands quicker design cycles, where extensive use of standard digital cells and even automated place-and-route tools for layout is preferred [1]. The proposed transmitter leverages a polar architecture with synthesized digital-to-time converter (DTC) wideband phase modulator, an all-digital PLL and a digital PA with matching network implemented on a flip-chip package to enable single-chip integration in 14nm trigate/finFET technology for IoT and wearable SoCs.
Year
Venue
Field
2017
ISSCC
Phase-locked loop,Transmitter,Wideband,Transceiver,System on a chip,Wearable computer,Computer science,AC power,Electronic engineering,Time to market,Electrical engineering,Embedded system
DocType
Citations 
PageRank 
Conference
2
0.44
References 
Authors
5
22
Name
Order
Citations
PageRank
Paolo Madoglio19113.34
Hongtao Xu262.57
Kailash Chandrashekar3477.21
Luis Cuellar4273.81
Muhammad Faisal5476.63
Yee William Li6202.27
Hyung Seok Kim754456.03
Khoa Minh Nguyen891.63
Yulin Tan9172.73
Brent R. Carlton10578.67
Vaibhav A. Vaidya11224.28
Yanjie Wang127310.93
Thomas Tetzlaff1320.78
Satoshi Suzuki14202.48
Amr Fahim1520.78
p seddighrad1620.78
Jianyong Xie1720.44
Zhichao Zhang18218.03
Divya Shree Vemparala1920.44
Ashoke Ravi2017626.87
Stefano Pellerano2119132.98
Yorgos Palaskas2222632.58