Name
Abstract | ||
|---|---|---|
Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability to independently control the data rate of each lane in a multi-lane transceiver with fine granularity is also valuable [1,2]. The implementation of such transceivers would require analog front-ends and clocking circuits that can operate over a wide range of frequencies. As a result, compared to transceivers that are optimized to operate at one single data rate, flexible-rate transceivers are power and area hungry [1]. Because a single PLL cannot generate clocks across the entire interface operating range, [1,2] use multiple LC tanks, carefully optimized waveform shaping circuits, power hungry clock distribution, and complex frequency planning methods. |
Year | Venue | Field |
|---|---|---|
2017 | ISSCC | Serial communication,Phase-locked loop,Waveform shaping,Transceiver,Computer science,Electronic engineering,Modulation,CMOS,Jitter,Electronic circuit,Electrical engineering |
DocType | Citations | PageRank |
Conference | 1 | 0.37 |
References | Authors | |
3 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Romesh Kumar Nandwana | 1 | 45 | 10.36 |
| Saurabh Saxena | 2 | 174 | 16.84 |
| Ahmed Elkholy | 3 | 77 | 16.19 |
| Mrunmay Talegaonkar | 4 | 123 | 15.61 |
| Junheng Zhu | 5 | 2 | 3.48 |
| Woo-Seok Choi | 6 | 105 | 12.58 |
| Ahmed Elmallah | 7 | 22 | 5.78 |
| Pavan Kumar Hanumolu | 8 | 554 | 84.82 |