Name
Title | ||
|---|---|---|
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology |
Abstract | ||
|---|---|---|
Demand for highly energy-efficient hardware for the inference computation of deep neural networks is increasing. Ultimately, fully spatially unrolled architecture where each distributed weight memory has a processing element (PE) for its exclusive use is the most energy-efficient solution because i) it can completely eliminate the energy-hungry data moving for weight fetching, and ii) PEs can consist only of combinational logics generally consuming less power than flip-flops. However, this strategy has not been applied because it requires a prohibitively huge amount of both area and hardware resources. We propose TDNN, which enables the fully spatially unrolled architecture by using 3D stacked ReRAM and the time-domain analog-digital mixed-signal processing that uses delay time as signal. In TDNN, a PE that performs synaptic operation is composed of only 12 logic transistors, which are equivalent to 3 gates. The proof-of-concept chip with SRAM instead of ReRAM shows unprecedentedly high energy efficiency of 48.2 TSop/s/W. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ASSCC.2016.7844126 | 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
Keywords | Field | DocType |
deep learning,convolutional neural network,neuromorphic computing,ReRAM | Logic gate,Computer science,Neuromorphic engineering,Electronic engineering,Real-time computing,Time delay neural network,Artificial intelligence,Deep learning,Artificial neural network,Static random-access memory,CMOS,Chip,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5090-3701-8 | 2 | 0.42 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Miyashita | 1 | 72 | 9.99 |
| Shouhei Kousai | 2 | 127 | 18.37 |
| Tomoya Suzuki | 3 | 24 | 3.37 |
| jun deguchi | 4 | 15 | 2.49 |