Daisuke Miyashita - Citegraph

Author Info

Name	Affiliation	Papers
DAISUKE MIYASHITA	Toshiba, Kawasaki, Kanagawa, Japan	20
Collaborators	Citations	PageRank
66	72	9.99
Referers	Referees	References
284	382	76

Search Limit

100382

Publications (20 rows)

Collaborators (66 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Revisiting a kNN-Based Image Classification System with High-Capacity Storage.	0	0.34	2022
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization	0	0.34	2021
Weight Compression Mac Accelerator For Effective Inference Of Deep Learning	0	0.34	2020
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems	0	0.34	2019
Post Training Weight Compression with Distribution-based Filter-wise Quantization Step	1	0.35	2019
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision	0	0.34	2018
A 12.8 Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems	0	0.34	2018
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing.	12	1.01	2017
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology	2	0.42	2016
Convolutional Neural Networks using Logarithmic Data Representation.	38	1.45	2016
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension	1	0.38	2014
A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS.	1	0.36	2013
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing.	5	0.76	2013
A-70 Dbm-Sensitivity 522 Mbps 0.19 Nj/Bit-Tx 0.43 Nj/Bit-Rx Transceiver For Transferjet (Tm) Soc In 65 Nm Cmos	0	0.34	2013
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.	5	0.63	2012
A -104 Dbc/Hz In-Band Phase Noise 3 Ghz All Digital Pll With Phase Interpolation Based Hierarchical Time To Digital Converter	0	0.34	2012
A Low-Noise And Highly-Linear Transmitter With Envelope Injection Pre-Power Amplifier For Multi-Mode Radio	0	0.34	2011
A Fully Integrated 2 X 1 Dual-Band Direct-Conversion Mobile Wimax Transceiver With Dual-Mode Fractional Divider And Noise-Shaping Transimpedance Amplifier In 65 Nm Cmos	5	0.72	2010
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner.	2	0.52	2009
Monolithically Integrated Mach-Zehnder Interferometer All-Optical Switches By Selective Area Movpe	0	0.34	2006