Paper Info
Title
Efficient Critical Path Selection Under a Probabilistic Delay Model.
Abstract
In this paper, an approach to select critical paths using a probabilistic delay model is presented. Paths through each fault site are selected to effectively test a device for small delay defects that may occur due to random process shifts in different pockets of the physical layout. Experimental evaluation shows significant improvement in time performance and quality of selected paths over existing work.
Year
DOI
Venue
2017
10.1145/3060403.3060468
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
Path delay faults, Delay testing, Critical paths
Delay calculation,Network delay,Computer science,Stochastic process,Real-time computing,Probabilistic logic,Critical path method,Elmore delay
Conference
Citations 
PageRank 
References 
2
0.40
11
Authors
2
Name
Order
Citations
PageRank
Ahish Mysore Somashekar171.90
Spyros Tragoudas262588.87