Name
Title | ||
|---|---|---|
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources |
Abstract | ||
|---|---|---|
The memory wall continues to be a major performance bottleneck. While small on-die caches have been effective so far in hiding this bottleneck, the ever-increasing footprint of modern applications renders such caches ineffective. Recent advances in memory technologies like embedded DRAM (eDRAM) and High Bandwidth Memory (HBM) have enabled the integration of large memories on the CPU package as an additional source of bandwidth other than the DDR main memory. Because of limited capacity, these memories are typically implemented as a memory-side cache. Driven by traditional wisdom, many of the optimizations that target improving system performance have been tried to maximize the hit rate of the memory-side cache. A higher hit rate enables better utilization of the cache, and is therefore believed to result in higher performance. In this paper, we challenge this traditional wisdom and present DAP, a Dynamic Access Partitioning algorithm that sacrifices cache hit rates to exploit under-utilized bandwidth available at main memory. DAP achieves a near-optimal bandwidth partitioning between the memory-side cache and main memory by using a light-weight learning mechanism that needs just sixteen bytes of additional hardware. Simulation results show a 13% average performance gain when DAP is implemented on top of a die-stacked memory-side DRAM cache. We also show that DAP delivers large performance benefits across different implementations, bandwidth points, and capacity points of the memory-side cache, making it a valuable addition to any current or future systems based on multiple heterogeneous bandwidth sources beyond the on-chip SRAM cache hierarchy. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/HPCA.2017.46 | 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) |
Keywords | Field | DocType |
DRAM cache,memory system bandwidth,access partitioning | Cache pollution,Computer science,CPU cache,Cache,Parallel computing,Cache-only memory architecture,Real-time computing,Cache algorithms,Page cache,Cache coloring,Bus sniffing | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-5090-4986-8 | 1 |
PageRank | References | Authors |
0.35 | 27 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jayesh Gaur | 1 | 108 | 6.98 |
| Mainak Chaudhuri | 2 | 300 | 18.86 |
| Pradeep Ramachandran | 3 | 1 | 1.36 |
| Sreenivas Subramoney | 4 | 127 | 13.60 |