Title
A scaling-less Newton-Raphson pipelined implementation for a fixed-point inverse square root operator
Abstract
The inverse square root is a common operation in digital signal processing architectures, in particular when matrix inversions are required. The Newton-Raphson algorithm is usually used, either in floating or in fixed-point formats. With the former format, the well-known fast inverse square root computation is based on a 32-bit integer constant, which is allowed by the standardized format of the mantissa. For the fixed-point format, there are many possibilities, which usually force a design with scaling of the input in order to respect a pre-determined work range. Having the input in a known range makes it possible to compute a first approximation with coefficients stored in memory. In this paper, a novel generic architecture which does not require scaling is proposed. This design is totally pipelined, ROM-less and can be directly used in any architecture. The implementation is optimized to reach the maximum clock frequency offered by the DSP cells of Xilinx FPGAs. This frequency is higher than the one available by using memory blocks.
Year
DOI
Venue
2017
10.1109/NEWCAS.2017.8010129
2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)
Keywords
Field
DocType
scaling-less Newton-Raphson pipelined implementation,fixed-point inverse square root operator,digital signal processing architectures,matrix inversion,fixed-point formats,floating-point formats,fast inverse square root computation,approximation,generic architecture,clock frequency,Xilinx FPGA,memory blocks
Fast inverse square root,Digital signal processing,Computer science,Field-programmable gate array,Electronic engineering,Fixed point,Scaling,Significand,Clock rate,Newton's method
Conference
ISSN
ISBN
Citations 
2472-467X
978-1-5090-4992-9
1
PageRank 
References 
Authors
0.37
6
4
Name
Order
Citations
PageRank
Erwan Libessart131.09
Matthieu Arzel26915.10
Cyril Lahuec3299.17
F. P. Andriulli475.65