Name
Abstract | ||
|---|---|---|
Cache tuning has been widely studied in CPUs, and shown to achieve substantial energy savings, with minimal performance degradations. However, cache tuning has yet to be explored in General Purpose Graphics Processing Units (GPGPU), which have emerged as efficient alternatives for general purpose high-performance computing. In this paper, we explore autonomic cache tuning for GPGPUs, where the cache configurations (cache size, line size, and associativity) can be dynamically specialized/tuned to the executing applications' resource requirements. We investigate cache tuning for both the level one (L1) and level two (L2) caches to derive insights into which cache level offers maximum optimization benefits. To illustrate the optimization potentials of autonomic cache tuning in GPGPUs, we implement a tuning heuristic that can dynamically determine each application's best L1 data cache configurations during runtime. Our results show that application-specific autonomic L1 data cache tuning can reduce the average energy delay product (EDP) and improve the performance by 16.5% and 18.8%, respectively, as compared to a static cache. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ICCAC.2017.17 | 2017 International Conference on Cloud and Autonomic Computing (ICCAC) |
Keywords | DocType | ISBN |
Graphics processing unit,GPGPU,GPU cache management,high performance computing,configurable caches,cache tuning,cache memories,low-power design,low-power embedded systems,adaptable hardware | Conference | 978-1-5386-2319-0 |
Citations | PageRank | References |
0 | 0.34 | 17 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sam Gianelli | 1 | 2 | 0.72 |
| Edward Richter | 2 | 0 | 0.34 |
| Diego Jiménez | 3 | 0 | 0.34 |
| Hugo Valdez | 4 | 0 | 0.34 |
| Tosiron Adegbija | 5 | 54 | 14.45 |
| Ali Akoglu | 6 | 157 | 29.40 |