Name
Abstract | ||
|---|---|---|
A voltage domain correction technique is proposed to mitigate the timing skew errors in time interleaved (TI) analog to digital converters (ADCs). The proposed technique exploits the fact that any timing skew in the sampling edge of a clock results in a corresponding error in sampled voltage that propagates through the ADC. The technique intends to cancel this voltage error by applying a correction voltage at the input sampling network in a TI-ADC. The effectiveness of the technique is demonstrated by using behavioral models of a 14-bit 500MS/s 2 channel TI-pipelined-ADC. |
Year | Venue | Keywords |
|---|---|---|
2017 | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | Time Interleaving, Background Calibration, Timing Skew Calibration |
Field | DocType | ISSN |
Flight dynamics (spacecraft),Computer science,Control theory,Voltage,Communication channel,Electronic engineering,To digital converter,Bandwidth (signal processing),Sampling (statistics),Skew,Calibration | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Praveen Kumar Venkatachala | 1 | 3 | 4.79 |
| Ahmed ElShater | 2 | 7 | 3.98 |
| Yang Xu | 3 | 118 | 41.02 |
| Manar El-Chammas | 4 | 1 | 0.72 |
| Un-Ku Moon | 5 | 836 | 140.98 |