Name
Title | ||
|---|---|---|
Reducing Power, Area, And Delay Of Threshold Logic Gates Considering Non-Integer Weights |
Abstract | ||
|---|---|---|
This paper shows that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of non-integer weights is proposed. Experimental results show that the transistor count reduction results in significant reduction in power dissipation and delay. |
Year | Venue | Field |
|---|---|---|
2017 | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | Transistor count,Diode–transistor logic,Logic gate,Sequential logic,Pass transistor logic,Control theory,AND-OR-Invert,Logic optimization,Electronic engineering,Logic family,Mathematics |
DocType | ISSN | Citations |
Conference | 0271-4302 | 0 |
PageRank | References | Authors |
0.34 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seyed Nima Mozaffari | 1 | 6 | 1.84 |
| Spyros Tragoudas | 2 | 625 | 88.87 |
| Themistoklis Haniotakis | 3 | 97 | 16.09 |