Name
Abstract | ||
|---|---|---|
This paper presents an 11bit 200MS/s SAR-assisted pipeline ADC with a 2.5bit front end stage and two time-interleaved 9bit sub-SAR ADCs, implemented in 65nm CMOS process. The bias-enhanced ring amplifier works as the residue amplifier for power efficiency and large signal swing. Two self-biased inverter stages are designed in the ring amplifier to maintain the closed loop stability. The SAR ADCs with custom capacitor arrays are featured by l.5bit acceleration in the second quantization step. With the least-mean-square algorithm calibration, this ADC achieves an ENOB of 9.5bit and a FoM of 15.7fJ/conv-step at a 2.4MHz input signal sampled at 200MHz. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISCAS.2017.8050244 | 2017 IEEE International Symposium on Circuits and Systems (ISCAS) |
Keywords | Field | DocType |
Pipeline-SAR ADC,bias-enhanced ring amplifier,time-interleaved ADC,accelerated SAR ADC | Electrical efficiency,Front and back ends,Inverter,Capacitor,Computer science,Control theory,Direct-coupled amplifier,Electronic engineering,Effective number of bits,Transistor,Electrical engineering,Amplifier | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-5090-1427-9 | 0 |
PageRank | References | Authors |
0.34 | 3 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongzhen Chen | 1 | 3 | 4.82 |
| Jingjing Wang | 2 | 2 | 1.09 |
| Hang Hu | 3 | 2 | 3.12 |
| Fan Ye | 4 | 63 | 21.55 |
| Junyan Ren | 5 | 154 | 41.40 |