Name
Abstract | ||
|---|---|---|
The adoption of the digital/time converter (DTC) circuit has improved the performance of ΔΣ fractional-N phase-locked loops (PLLs). Accurate cancellation of ΔΣ quantization error via the DTC requires an automatic calibration made by an LMS loop. A high-order ΔΣ speeds up calibration convergence and improves PLL spectral purity, though at the price of larger quantization error and wider DTC range. To overcome this problem, we propose an innovative parallel segmentation scheme which reduces the range of quantization error without compromising spectral purity and convergence speed. The effectiveness of the proposed segmentation scheme is demonstrated via behavioral-level simulations of a digital PLL and compared to the conventional cascaded segmentation scheme. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISCAS.2017.8050285 | 2017 IEEE International Symposium on Circuits and Systems (ISCAS) |
Keywords | Field | DocType |
segmentation scheme,delta-sigma fractional-N phase-locked loops,DTC-based delta-sigma fractional-N PLL,digital-time converter circuit,DTC circuit,delta-sigma quantization error | Convergence (routing),Spectral purity,Phase-locked loop,Computer science,Control theory,Segmentation,Electronic engineering,CMOS,Quantization (signal processing),Calibration | Conference |
ISBN | Citations | PageRank |
978-1-5090-1427-9 | 0 | 0.34 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tuan Minh Vo | 1 | 0 | 0.34 |
| Carlo Samori | 2 | 349 | 39.76 |
| Andrea L. Lacaita | 3 | 320 | 42.41 |
| Salvatore Levantino | 4 | 351 | 43.23 |