Name
Abstract | ||
|---|---|---|
Neural networks have been widely used in a large range of domains, researchers tune numbers of layrs, neurons and synapses to adapt various applications. As a consequence, computations and memory of neural networks models are both intensive. As large requirements of memory and computing resources, it is difficult to deploy neural networks on resource-limited platforms. Sparse neural networks, which prune redundant neurons and synapses, alleviate computation and memory pressure. However, conventional accelerators cannot benefit from the sparse feature.
In this paper, we propose a high-performance FPGA accelerator for sparse neural networks which utilizes eliminate computations and storage space. This work compresses sparse weights and processes compressed data directly. Experimental results demonstrate that our accelerator will reduce 50% and 10% storage of convolutional and full-connected layers, and achieve 3x speedup of performance over an optimized conventional FPGA accelerator.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3125501.3125510 | CASES |
Keywords | Field | DocType |
high-performance FPGA accelerator,sparse neural networks,synapses,sparse weights,compressed data processing,full-connected layers,storage space,optimized conventional FPGA accelerator,memory pressure,redundant neurons | Computer science,Work in process,Parallel computing,Field-programmable gate array,Artificial intelligence,Deep learning,Artificial neural network,Computation,Speedup | Conference |
ISBN | Citations | PageRank |
978-1-4503-5184-3 | 0 | 0.34 |
References | Authors | |
4 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuntao Lu | 1 | 0 | 0.68 |
| Lei Gong | 2 | 1 | 2.47 |
| Chongchong Xu | 3 | 7 | 4.63 |
| Fan Sun | 4 | 6 | 3.27 |
| Yiwei Zhang | 5 | 52 | 12.65 |
| Chao Wang | 6 | 372 | 62.24 |
| Xuehai Zhou | 7 | 551 | 77.54 |