Yiwei Zhang - Citegraph

Author Info

Name	Affiliation	Papers
YIWEI ZHANG	ZTE IC Design Co., Ltd., Shenzhen, China 518057	32
Collaborators	Citations	PageRank
94	52	12.65
Referers	Referees	References
177	548	205

Search Limit

100548

Publications (32 rows)

Collaborators (94 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Performance Analysis and Optimization of LDM-Based Layered Multicast	0	0.34	2022
Distributed Sliding Mode Fault-Tolerant LFC for Multiarea Interconnected Power Systems under Sensor Fault	0	0.34	2022
Using LDM-based Layered Multicast to Enhance System Capacity	0	0.34	2021
DECISION TREE BASED INTER PARTITION TERMINATION FOR AV1 ENCODING	0	0.34	2021
A Generative Compression Framework For Low Bandwidth Video Conference	1	0.37	2021
Private Proximity Retrieval Codes	0	0.34	2021
Look, Listen, and Act: Towards Audio-Visual Embodied Navigation	3	0.46	2020
Overview of Physical Layer Enhancement for 5G Broadcast in Release 16	6	0.69	2020
Orthogonalizing The Activity Of Two Neural Units For 2d Cursor Movement Control	0	0.34	2020
Watch, Reason and Code: Learning to Represent Videos Using Program	0	0.34	2019
Detection Based Defense Against Adversarial Examples From The Steganalysis Point Of View	4	0.41	2019
On The Access Complexity Of Pir Schemes	0	0.34	2018
Computer Vision Based and FPRank Based Tag Recommendation for Social Popularity Enhancement	0	0.34	2018
Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only).	0	0.34	2018
Adversarial Examples Against Deep Neural Network based Steganalysis.	5	0.41	2018
New Theoretical Bounds and Constructions of Permutation Codes under Block Permutation Metric.	0	0.34	2018
UniCNN: A Pipelined Accelerator Towards Uniformed Computing for CNNs.	0	0.34	2018
A new accurate image denoising method based on sparse coding coefficients	0	0.34	2018
A Power-Efficient Accelerator Based on FPGAs for LSTM Network	2	0.37	2017
Invertible binary matrices with maximum number of 2-by-2 invertible submatrices.	2	0.48	2017
A Power-Efficient Accelerator for Convolutional Neural Networks	2	0.38	2017
Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network	0	0.34	2017
OmniGraph: A Scalable Hardware Accelerator for Graph Processing	0	0.34	2017
A general private information retrieval scheme for MDS coded databases with colluding servers.	12	0.64	2017
A high-performance FPGA accelerator for sparse neural networks: work-in-progress	0	0.34	2017
A High-Performance Accelerator for Large-Scale Convolutional Neural Networks	0	0.34	2017
On private information retrieval array codes.	4	0.55	2016
Three-Dimensional Path Planning Based On Ant Colony Algorithm With Potential Field For Rotary-Wing Flying Robot	0	0.34	2015
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic	4	0.58	2013
A Novel Approach To Selecting Contractor In Agent-Based Multi-Sensor Battlefield Reconnaissance Simulation	0	0.34	2012
Fault analysis of Trivium	2	0.40	2012
Enhanced Correlation Power Analysis Attack on Smart Card	5	0.48	2008