Name
Abstract | ||
|---|---|---|
Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms introduce delays in the packet latency. This paper proposes the use of multiple paths as a way to reduce latency due to the impact of retransmissions in critical systems, i.e., where latency is a critical issue. The experimental results show that the use of multiple paths, minimal or not, enable to decrease the impact caused by retransmissions in 25% and 20% of the average packet latency for 22 and 65 nm CMOS technologies, respectively. Moreover, the proposed technique has a low impact on the average latency of the entire network and can contribute to a greater adaptability of faults on links.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3109984.3109985 | SBCCI '17: 30th Symposium on Integrated Circuits and Systems Design
Fortaleza
Ceará
Brazil
August, 2017 |
Keywords | Field | DocType |
Multiple paths, Fault tolerance, Network-on-Chip | Adaptability,Digital electronics,Computer science,Latency (engineering),Retransmission,Network packet,Network on a chip,CMOS,Real-time computing,Fault tolerance,Distributed computing | Conference |
ISBN | Citations | PageRank |
978-1-4503-5106-5 | 0 | 0.34 |
References | Authors | |
19 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ronaldo T. P. Milfont | 1 | 0 | 0.34 |
| Rafael Mota | 2 | 4 | 1.78 |
| Joao Marcelo Ferreira | 3 | 8 | 2.22 |
| Paulo CéSar Cortez | 4 | 82 | 8.67 |
| Cesar A. M. Marcon | 5 | 120 | 28.83 |
| Daniel A. B. Tavares | 6 | 0 | 0.68 |
| Jarbas Silveira | 7 | 20 | 6.62 |