Name
Title | ||
|---|---|---|
Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution |
Abstract | ||
|---|---|---|
Sub-threshold circuit is a promising circuit design style for IoT application, but the timing closure, especially hold timing fixing is a big challenge for designers. This paper proposes a mathematical method to estimate the number of insertion inverters/buffers for hold timing fixing in each short path. Firstly, the distribution of path delay is rigorously proved to be lognormal distribution in the sub-threshold region, considering different supply voltages, cell driven strengths and load capacitances. Secondly, the number of insertion is derived based on the target yield. Finally, Monte Carlo Spice simulation under SMIC 40nm CMOS process demonstrates that theory can estimate the number of insertion inverters/buffers. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/PATMOS.2017.8106972 | 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) |
Keywords | Field | DocType |
IoT,circuit design,sub-threshold circuit,lognormal distribution,size 40.0 nm | Monte Carlo method,Capacitance,Control theory,Computer science,Spice,Voltage,Internet of Things,Circuit design,Electronic engineering,Log-normal distribution,Timing closure | Conference |
ISSN | ISBN | Citations |
2474-5456 | 978-1-5090-6463-2 | 0 |
PageRank | References | Authors |
0.34 | 9 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jingjing guo | 1 | 1 | 6.11 |
| Min Wang | 2 | 169 | 36.41 |
| Jizhe Zhu | 3 | 2 | 0.77 |
| Xinning Liu | 4 | 8 | 4.02 |
| Jun Yang | 5 | 82 | 40.03 |