Name
Abstract | ||
|---|---|---|
Compute-intensive GPU architectures allow the use of high-order 3D stencils for better computational accuracy. These stencils are usually compute-bound. While current state-of-the-art register allocators are satisfactory for most applications, they are unable to effectively manage register pressure for such complex high-order stencils, resulting in a sub-optimal code with a large number of register spills. We develop an optimization framework that models stencils as a forest of trees and performs statement reordering to reduce register use. The effectiveness of the approach is demonstrated through experimental results on several high-order stencils. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/PACT.2017.40 | 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) |
Keywords | Field | DocType |
high-order stencils,register pressure,GPU computing | Computer science,Parallel computing,Bandwidth (signal processing),Allocator,Benchmark (computing) | Conference |
ISSN | ISBN | Citations |
1089-795X | 978-1-5090-6765-7 | 1 |
PageRank | References | Authors |
0.35 | 3 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prashant Singh Rawat | 1 | 40 | 4.51 |
| Aravind Sukumaran-Rajam | 2 | 50 | 12.03 |
| Atanas Rountev | 3 | 1999 | 108.60 |
| Fabrice Rastello | 4 | 482 | 38.30 |
| Louis-noël Pouchet | 5 | 880 | 47.61 |
| P. Sadayappan | 6 | 4821 | 344.32 |