Name
Title | ||
|---|---|---|
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. |
Abstract | ||
|---|---|---|
In this paper, we propose an ultra-lowvoltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low V-t (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB macro. Process voltage temperature (PVT) compensation is performed on-chip by an adaptive back biasing (ABB) generator. At 0.4V, the proposed SRAM can operate at 80 MHz and reaches access energy of 28 fJ/bit including the ABB generator in closed-loop operation. |
Year | Venue | Keywords |
|---|---|---|
2017 | ESSCIRC 2017 - 43RD IEEE EUROPEAN SOLID STATE CIRCUITS CONFERENCE | SRAM,Ultra-low power,Ultra-low voltage,Importance sampling,Ultra-low power diodes |
Field | DocType | Citations |
Silicon on insulator,Leakage (electronics),Computer science,Failure rate,Static random-access memory,CMOS,Electronic engineering,Transistor,Macro,Electrical engineering,Biasing | Conference | 0 |
PageRank | References | Authors |
0.34 | 5 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Haine | 1 | 0 | 1.35 |
| Quoc-Khoi Nguyen | 2 | 0 | 0.34 |
| François Stas | 3 | 6 | 2.87 |
| Ludovic Moreau | 4 | 6 | 1.91 |
| Denis Flandre | 5 | 316 | 70.47 |
| David Bol | 6 | 162 | 27.67 |