Title
The Next Generation of Exascale-Class Systems: The ExaNeSt Project
Abstract
The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an Euro-pean Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.
Year
DOI
Venue
2017
10.1109/DSD.2017.20
2017 Euromicro Conference on Digital System Design (DSD)
Keywords
Field
DocType
EU H2020 research framework,Linux-based power efficient 64-bit ARM processors clusters,ExaNeSt consortium pools,physical rack prototype,low-latency interconnect,storage nonvolatile memory architecture,cooling system,Euro-pean Exascale-class supercomputer,exanest project,exascale-class systems,storage capacity 64 bit
ARM architecture,Status report,Architecture,Supercomputer,Computer science,Field-programmable gate array,Network topology,Real-time computing,Interconnection,Conceptual framework,Operating system
Conference
ISBN
Citations 
PageRank 
978-1-5386-2147-9
2
0.39
References 
Authors
2
18