Name
Abstract | ||
|---|---|---|
With the increase of CMP (Chip-Multiprocessor) scale, moving data to computation on chip becomes more expensive. Accordingly, moving computation to data has potential to improve efficiency. We propose an in-place computation co-design of many-simple-core CMP for irregular applications. The computing paradigm is that an application's critical irregular data (or part of them) is partitioned into on-chip memory-slices and each slice is delegated by an adjacent core. From the hardware aspect, it divides cores into two groups with load balancing; each group is responsible for accessing off-chip data or irregular data respectively. Moreover, L2 caches are replaced with scratchpads and intra-core message-passing is supported by hardware. Accordingly, algorithms of some typical irregular application kernels are presented, including Breadth-First Search, hash-map, Sparse Matrix-Vector Multiplication and data-walk. Simulations show that, compared with conventional implementations based on cache-coherence (CC), it can improve the performance and energy-efficiency significantly. The limitation is also discussed. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ICPPW.2017.23 | 2017 46th International Conference on Parallel Processing Workshops (ICPPW) |
Keywords | Field | DocType |
in-place computation,chip-multiprocessor,irregular applications,message passing | Algorithm design,System on a chip,Load balancing (computing),Irregular Z-buffer,Computer science,Parallel computing,Chip,Multiplication,Message passing,Distributed computing,Computation | Conference |
ISSN | ISBN | Citations |
1530-2016 | 978-1-5386-1045-9 | 0 |
PageRank | References | Authors |
0.34 | 36 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Youhui Zhang | 1 | 202 | 28.36 |
| Youyang Zhang | 2 | 0 | 0.34 |
| Yanhua Li | 3 | 12 | 2.68 |
| Xiang Fei | 4 | 1 | 1.36 |
| Weimin Zheng | 5 | 1889 | 182.48 |