Name
Abstract | ||
|---|---|---|
Layout-level gate or routing camouflaging techniques have attracted interest as countermeasures against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gate or routing components are camouflaged, and each camouflaged component layout can implement one of a few different functions or connections. The security of camouflaging relies on the d... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCAD.2017.2652220 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Logic gates,Reverse engineering,Logic functions,Standards,Integrated circuit modeling,Imaging | Logic gate,Sequential logic,Logic optimization,Computer science,Reverse engineering,Theoretical computer science,Combinational logic,Electronic engineering,Real-time computing,Logic family,Electronic circuit,Speedup | Journal |
Volume | Issue | ISSN |
36 | 10 | 0278-0070 |
Citations | PageRank | References |
12 | 0.58 | 30 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cunxi Yu | 1 | 98 | 9.64 |
| Zhang, Xiangyu | 2 | 22 | 4.16 |
| Duo Liu | 3 | 78 | 4.08 |
| Maciej J. Ciesielski | 4 | 629 | 74.80 |
| Daniel E. Holcomb | 5 | 462 | 31.63 |