Name
Title | ||
|---|---|---|
Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. |
Abstract | ||
|---|---|---|
After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware ove... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCAD.2016.2611505 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Through-silicon vias,Computer architecture,Bridge circuits,Hardware,Testing,Logic gates,Resistance | Architecture,Logic gate,Comparator,Computer science,Resistive touchscreen,Voltage,Test quality,Electronic engineering,Stacking,Embedded system | Journal |
Volume | Issue | ISSN |
36 | 10 | 0278-0070 |
Citations | PageRank | References |
1 | 0.37 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young Woo Lee | 1 | 9 | 5.76 |
| Hyeonchan Lim | 2 | 2 | 2.45 |
| Sungho Kang | 3 | 436 | 78.44 |