Name
Abstract | ||
|---|---|---|
The eXecutable Micro-Architectural Specification (xMAS) language developed in recent years finds an effective way to model on-chip communication fabrics and enables performance-bound analysis with network calculus at the micro-architectural level. For network-on-Chip (NoC) performance analysis, model validation is essential to ensure correctness and accuracy. In order to facilitate the xMAS modeling and corresponding analysis validation, this work presents a unified platform based on xMAS in Simulink. The platform provides a friendly graphical user interface for xMAS modeling and parameter setup by taking advantages of the Simulink modeling environment. The regulator and latency-rate sever are added to the xMAS primitive set to support typical flow and service behaviors. Hierarchical model build-up and Verilog-HDL code generation are essentially supported to manage complex models and to conduct cycle-accurate bit-accurate simulations. Based on the generated simulation models of xMAS, this tool is applied to evaluate the tightness of analytical delay bound results. We demonstrate the application as well as the work flow of the xMAS tool through a two-agent communication example and an all-to-one communication example with a tree topology.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3005446 | ACM Trans. Model. Comput. Simul. |
Keywords | Field | DocType |
Performance analysis, network calculus, network on chip, simulink | Mathematical optimization,Computer science,Simulation,Correctness,Network on a chip,Code generation,Network topology,Graphical user interface,Network calculus,Hierarchical database model,Executable,Distributed computing | Journal |
Volume | Issue | ISSN |
27 | 3 | 1049-3301 |
Citations | PageRank | References |
1 | 0.37 | 36 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xueqian Zhao | 1 | 151 | 10.47 |
| Zhonghai Lu | 2 | 1063 | 100.12 |