Title
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM.
Abstract
This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed...
Year
DOI
Venue
2017
10.1109/TCSII.2015.2483158
IEEE Transactions on Circuits and Systems II: Express Briefs
Keywords
Field
DocType
Delays,SDRAM,Steady-state,System-on-chip,Computer architecture,Threshold voltage,Simulation
System on a chip,Memory bandwidth,Communication channel,Electronic engineering,CMOS,Input/output,Threshold voltage,Mathematics,CAS latency,Swing
Journal
Volume
Issue
ISSN
64
10
1549-7747
Citations 
PageRank 
References 
0
0.34
1
Authors
3
Name
Order
Citations
PageRank
Jungtaek You110.70
Junyoung Song24011.42
Chulwoo Kim339774.58