Name
Abstract | ||
|---|---|---|
This paper presents an advanced DAG-based algorithm for datapath synthesis that targets area minimization using logic-level resource sharing. The problem of identifying common specification logic is formulated using unweighted graph isomorphism problem, in contrast to a weighted graph isomorphism using AIGs. In the context of gate-level datapath circuits, our algorithm solves the unweighted graph isomorphism problem in linear time. The experiments are conducted within an industrial synthesis flow that includes the complete high-level synthesis, logic synthesis and placement and route procedures. Experimental results show a significant runtime improvements compared to the existing datapath synthesis algorithms.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/iccad.2017.8203808 | ICCAD |
Keywords | DocType | Volume |
Logic synthesis,datapath synthesis,resource sharing,graph isomorphism | Conference | abs/1708.09597 |
ISSN | ISBN | Citations |
1933-7760 | 978-1-4503-5950-4 | 0 |
PageRank | References | Authors |
0.34 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cunxi Yu | 1 | 98 | 9.64 |
| Mihir R. Choudhury | 2 | 184 | 15.40 |
| Andrew Sullivan | 3 | 3 | 1.45 |
| Maciej J. Ciesielski | 4 | 629 | 74.80 |