Name
Abstract | ||
|---|---|---|
A new multiple-loop design technique for high-performance low-dropout (LDO) regulator designs has been proposed and successfully implemented in many commercial products for portable smart phone and tablet PC applications. The proposed LDO is composed of five loops that allows designers to obtain a good tradeoff between quiescent current and other performances, such as undershoot, overshoot, and so... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/JSSC.2017.2717922 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Transient response,Transient analysis,Parasitic capacitance,Regulators,Logic gates,Power transistors,Poles and zeros | Logic gate,Capacitor,Parasitic capacitance,Computer science,Power semiconductor device,Control theory,Voltage,Electronic engineering,Electrical engineering,Bandgap voltage reference,Low-dropout regulator,Biasing | Journal |
Volume | Issue | ISSN |
52 | 10 | 0018-9200 |
Citations | PageRank | References |
4 | 0.41 | 7 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Quoc-Hoang Duong | 1 | 4 | 0.75 |
| Huy-Hieu Nguyen | 2 | 54 | 7.46 |
| Jeong-Woon Kong | 3 | 4 | 0.75 |
| Hyun-Seok Shin | 4 | 4 | 0.41 |
| Yu-Seok Ko | 5 | 4 | 0.75 |
| Hwa-Yeol Yu | 6 | 4 | 0.41 |
| Yong Hee Lee | 7 | 46 | 7.09 |
| Chun-Hyeon Bea | 8 | 4 | 0.41 |
| Ho-Jin Park | 9 | 36 | 6.77 |