Multiple-Loop Design Technique for High-Performance Low-Dropout Regulator. | 4 | 0.41 | 2017 |
A 0.015-mm $^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology | 2 | 0.47 | 2017 |
Multiple-loop design technique for high-performance low dropout regulator | 0 | 0.34 | 2016 |
A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications | 0 | 0.34 | 2016 |
8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors | 12 | 0.98 | 2016 |
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS | 8 | 0.97 | 2015 |
A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS | 0 | 0.34 | 2015 |
A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation | 6 | 1.12 | 2014 |
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS | 1 | 0.36 | 2011 |
A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter | 1 | 0.41 | 2000 |
A DLL based 10-320 MHz clock synchronizer | 1 | 0.69 | 2000 |
A 1.4 V 10-bit 20 MSPS pipelined A/D converter | 1 | 0.35 | 2000 |