Name
Title | ||
|---|---|---|
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. |
Abstract | ||
|---|---|---|
This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency d... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/JSSC.2017.2744661 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Decision feedback equalizers,Decision feedback equalizers,Phase frequency detector,Detectors,Receivers,Local oscillators | Digitally controlled oscillator,Comparator,Computer science,Analog front-end,CMOS,Electronic engineering,Phase detector,Detector,Clock rate,Phase frequency detector | Journal |
Volume | Issue | ISSN |
52 | 12 | 0018-9200 |
Citations | PageRank | References |
2 | 0.40 | 7 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wahid Rahman | 1 | 6 | 1.61 |
| Danny Yoo | 2 | 62 | 7.08 |
| Joshua Liang | 3 | 3 | 1.12 |
| Ali Sheikholeslami | 4 | 416 | 54.27 |
| Hirotaka Tamura | 5 | 204 | 32.19 |
| Takayuki Shibasaki | 6 | 66 | 12.00 |
| Hisakatsu Yamaguchi | 7 | 64 | 10.20 |