Name
Abstract | ||
|---|---|---|
Sub-threshold circuit is a promising circuit design style for IoT application. This paper concentrated on the delay model based on the transient current model in the sub-threshold region. In order to deduce the path delay model, two ways are adopted, which are the coupling capacitance equivalence and the output waveform equivalence. The distribution of path delays is rigidly proven to be lognormal distribution in the sub-threshold region. Considering different supply voltages, cell driven strengths and load capacitances, the proposed model is also validated by Monte Carlo Spice simulation under SMIC 40 nm CMOS process. Experiments show that proposed model agrees with MC simulation results with error 0.448% under the condition of 0.4V and 99.7% probability, which proves the feasibility of the model. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1587/elex.14.20170390 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
sub-threshold circuit, lognormal distribution, delay model, variation analysis | Inverter,Computer science,Electronic engineering,Electronic circuit,Log-normal distribution | Journal |
Volume | Issue | ISSN |
14 | 11 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jingjing guo | 1 | 1 | 6.11 |
| Jizhe Zhu | 2 | 0 | 0.34 |
| Min Wang | 3 | 169 | 36.41 |
| Jianxin Nie | 4 | 0 | 0.34 |
| Xinning Liu | 5 | 8 | 4.02 |
| Wei Ge | 6 | 21 | 11.72 |
| Jun Yang | 7 | 82 | 40.03 |