Name
Abstract | ||
|---|---|---|
Power dissipation during scan testing of a systemon-chip can be significantly higher than that during functional mode, causing reliability and yield concerns. This paper proposes a logic cluster controllability (LoCCo)-based scan chain stitching methodology to achieve low-power testing. The scan chain stitching is made power aware by placing flip-flops with higher test combination requirements at ... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2017.2735864 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Controllability,Clocks,Algorithm design and analysis,Switches,Computer architecture,Testing,Discrete Fourier transforms | Image stitching,Algorithm design,Controllability,Computer science,Dissipation,Algorithm,Scan chain,Electronic engineering,Routing congestion,Real-time computing,CMOS,Computation | Journal |
Volume | Issue | ISSN |
25 | 11 | 1063-8210 |
Citations | PageRank | References |
1 | 0.36 | 25 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shalini Pathak | 1 | 1 | 0.36 |
| Anuj Grover | 2 | 10 | 6.49 |
| Mausumi Pohit | 3 | 1 | 1.03 |
| Nitin Bansal | 4 | 13 | 2.38 |