Name
Abstract | ||
|---|---|---|
Hardware invariants are known to facilitate bit-flip detection during post-silicon validation. In this paper, we present a fully automated SAT-based methodology for fast generation of hardware invariants by using the built-in pruning mechanisms within SAT solvers, namely learned clauses. These candidates are evaluated for their potential to detect bit-flips using a new incremental SAT-based approach. In addition to speeding-up the simulation-based approaches for invariant generation and evaluation, when compared to the known art, our results show improvements in both the number of flip-flops that can be covered for bit-flip detection, as well as for the on-chip area for the bit-flip detection unit.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ICCAD.2017.8203766 | ICCAD |
Keywords | Field | DocType |
Hardware Invariants,Post-Silicon Validation,Bit-flip Detection | Post-silicon validation,Computer science,Electronic engineering,Invariant (mathematics),Computer hardware,Detector | Conference |
ISSN | ISBN | Citations |
1933-7760 | 978-1-4503-5950-4 | 0 |
PageRank | References | Authors |
0.34 | 13 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pouya Taatizadeh | 1 | 11 | 2.26 |
| Nicola Nicolici | 2 | 807 | 59.91 |