Name
Abstract | ||
|---|---|---|
The need for higher throughput and lower communication latency in modern networks-on-chip (NoC) has led to low- and high-radix topologies that exploit the speed provided by on-chip wires-after appropriate wire engineering-to transfer flits over longer distances in a single clock cycle. In this paper, motivated by the same principle of fast link traversal, we propose the RapidLink NoC architecture,... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCSI.2017.2734689 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Network-on-chip,Delays,Elastic buffers,Throughput,Scalability,Network architecture | Tree traversal,Latency (engineering),Computer network,Electronic engineering,Network topology,Throughput,Cycles per instruction,Double data rate,Mathematics,Scalability,Network performance | Journal |
Volume | Issue | ISSN |
64 | 12 | 1549-8328 |
Citations | PageRank | References |
3 | 0.39 | 19 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Psarras, A. | 1 | 38 | 4.44 |
| Savvas Moisidis | 2 | 3 | 0.39 |
| Chrysostomos Nicopoulos | 3 | 835 | 50.37 |
| Giorgos Dimitrakopoulos | 4 | 215 | 27.31 |