Paper Info
Title
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs.
Abstract
Executing multiple applications on a single MPSoC brings the major challenge of satisfying multiple quality requirements regarding real-time, energy, and so on. Hybrid application mapping denotes the combination of design-time analysis with run-time application mapping. In this article, we present such a methodology, which comprises a design space exploration coupled with a formal performance analysis. This results in several resource reservation configurations, optimized for multiple objectives, with verified real-time guarantees for each individual application. The Pareto-optimal configurations are handed over to run-time management, which searches for a suitable mapping according to this information. To provide any real-time guarantees, the performance analysis needs to be composable and the influence of the applications on each other has to be bounded. We achieve this either by spatial or a novel temporal isolation for tasks and by exploiting composable networks-on-chip (NoCs). With the proposed temporal isolation, tasks of different applications can be mapped to the same resource, while, with spatial isolation, one computing resource can be exclusively used by only one application. The experiments reveal that the success rate in finding feasible application mappings can be increased by the proposed temporal isolation by up to 30% and energy consumption can be reduced compared to spatial isolation.
Year
DOI
Venue
2018
10.1145/3274665
ACM Transactions in Embedded Computing Systems
Keywords
DocType
Volume
Hybrid mapping, design space exploration, many-core, networks-on-chip, predictability
Journal
abs/1711.05932
Issue
ISSN
Citations 
5
1539-9087
1
PageRank 
References 
Authors
0.35
38
5
Name
Order
Citations
PageRank
Andreas Weichslgartner1527.16
Stefan Wildermann215626.00
Deepak Gangadharan3347.44
Michael Glaß451045.33
Jürgen Teich5159.70