Name
Abstract | ||
|---|---|---|
Image scaling is one of the widely used techniques in various portable devices to fit the image in their respective displays. Traditional image scaling architectures consume more power and hardware, making them inefficient for use in portable devices. In this paper, a low complexity image scaling algorithm is proposed. In the proposed algorithm, the target pixel is computed either by bilinear interpolation or by replication. The edge catching module in the architecture determines the method of computation which makes the design energy efficient. Further, algebraic manipulation is done and the resulting pipelined architecture shows significant reduction in hardware cost. In order to evaluate the efficacy, the proposed and existing algorithms are implemented in MATLAB and simulated using standard benchmark images. The proposed design is synthesized in Synopsys Design Compiler using 90-nm CMOS process which shows 43.3% reduced gate count and 25.9% reduction in energy over existing architectures without significant degradation in quality. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISVDAT.2016.8064888 | 2016 20th International Symposium on VLSI Design and Test (VDAT) |
Keywords | Field | DocType |
Image scaling,VLSI,Bilinear interpolation,Sharpening filter,Edge catching | Gate count,Algorithm design,Efficient energy use,Computer science,Interpolation,Electronic engineering,Compiler,Real-time computing,Pixel,Image scaling,Bilinear interpolation | Conference |
ISSN | ISBN | Citations |
2475-8620 | 978-1-5090-1423-1 | 1 |
PageRank | References | Authors |
0.37 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bharat Garg | 1 | 32 | 9.88 |
| V. N. S. K. Chaitanya Goteti | 2 | 1 | 0.37 |
| G. K. Sharma | 3 | 2 | 1.41 |