Name
Abstract | ||
|---|---|---|
This paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC2) concept based on memory architecture for data-intensive (imaging, ...) and secure (cryptography, ...) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally performed by an ALU. As a result, logic and arithmetic operations can be entirely executed within the memory unit leading to a significant reduction in power consumption related to the data transfer between memories and computing units. Moreover, the proposed computing circuit can perform extremely-parallel operations enabling the processing of large volume of data. A test case based on image processing application and using the saturating increment function is analytically modeled to compare conventional and DRC2-based approaches. It is demonstrated that DRC2-based approach provides a reduction of clock cycle number of up to 2x. Finally, potential applications and must-be-considered changes at different design levels are discussed. |
Year | Venue | Keywords |
|---|---|---|
2016 | 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC) | in-memory computing, computing architecture, programmable logic |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaya Can Akyel | 1 | 0 | 0.34 |
| Henri-pierre Charles | 2 | 62 | 13.45 |
| Julien Mottin | 3 | 1 | 0.68 |
| Bastien Giraud | 4 | 53 | 17.41 |
| Gregory Suraci | 5 | 0 | 0.34 |
| Sebastien Thuries | 6 | 27 | 7.32 |
| Jean-Philippe Noel | 7 | 16 | 5.00 |