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SEBASTIEN THURIES
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Name
Affiliation
Papers
SEBASTIEN THURIES
CEA Grenoble, LETI, F-38054 Grenoble, France
17
Collaborators
Citations
PageRank
107
27
7.32
Referers
Referees
References
108
255
60
Search Limit
100
255
Publications (17 rows)
Collaborators (100 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
3
0.45
2021
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters
0
0.34
2020
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning
0
0.34
2019
Advanced 3d Technologies And Architectures For 3d Smart Image Sensors
0
0.34
2019
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges
0
0.34
2018
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
0
0.34
2017
7.5 A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networks
2
0.58
2017
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits.
0
0.34
2017
Drc2: Dynamically Reconfigurable Computing Circuit Based On Memory Architecture
0
0.34
2016
Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes
0
0.34
2016
Opportunities brought by sequential 3D CoolCube™ integration
0
0.34
2016
Recent advances in 3D VLSI integration
0
0.34
2016
Intermediate BEOL process influence on power and performance for 3DVLSI
0
0.34
2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges
1
0.37
2015
A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
15
1.03
2015
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits
3
0.59
2015
3DCoB: A new design approach for Monolithic 3D Integrated circuits.
3
0.58
2014
1