Name
Abstract | ||
|---|---|---|
Probabilistic circuits are very attractive for the next generation ultra-low power designs. It is important to test probabilistic circuits because a defect in probabilistic circuit may increase the erroneous probability. However, there is no suitable fault model and test generation/compression technique for probabilistic circuits yet. In this paper, a probabilistic fault model is proposed for probabilistic circuits. The number of faults is linear to the gate count. A statistical method is proposed to calculate the repetition needed for each test pattern. An integer linear programming (ILP) method is presented to minimize total test length, while keeping the same fault coverage. Experiments on ISCAS'89 benchmark circuits show the total test length of our proposed ILP method is 64% shorter than a greedy method. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ATS.2017.17 | 2017 IEEE 26th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
Probabilistic Circuit,Test Pattern Compression,Fault Model | Gate count,Logic gate,Fault coverage,Computer science,Algorithm,Electronic engineering,Greedy algorithm,Integer programming,Probabilistic logic,Electronic circuit,Fault model | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5386-3516-2 | 0 |
PageRank | References | Authors |
0.34 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chih-Ming Chang | 1 | 0 | 0.34 |
| Kai-Jie Yang | 2 | 0 | 0.34 |
| James Chien-Mo Li | 3 | 187 | 27.16 |
| Hung Chen | 4 | 0 | 0.34 |