Name
Title | ||
|---|---|---|
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs |
Abstract | ||
|---|---|---|
We propose a supply current test method with a built-in sensor for detecting open defects on signal lines in CMOS logic circuits. The test method is based on an appearance time of dynamic supply current that flows when a test input vector is provided to a device under test. In addition, we propose a test pattern generation algorithm for the test method. An IC embedding the sensor is prototyped to examine the testability of the test method. We show by SPICE simulation and by some experiments with the IC that open defects that is undetectable by delay tests can be detected by the test method. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ATS.2017.53 | 2017 IEEE 26th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
open defect,IDDT testing,built-in sensor,test input generation algorithm | Testability,Test method,Logic gate,Embedding,Pattern generation,Device under test,Computer science,Spice,Electronic engineering,CMOS | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5386-3516-2 | 0 |
PageRank | References | Authors |
0.34 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayumu Kambara | 1 | 0 | 0.34 |
| Hiroyuki Yotsuyanagi | 2 | 70 | 19.04 |
| Daichi Miyoshi | 3 | 0 | 0.34 |
| Masaki Hashizume | 4 | 98 | 27.83 |
| Shyue-Kung Lu | 5 | 259 | 34.09 |