Name
Abstract | ||
|---|---|---|
With the advance of VLSI technology, the parameter shift due to device aging has increasingly impacts on the circuit yield and reliability. Because the aging effects may degrade circuit performance and cause circuit failure after a period of time, aging analysis is also required in the design flow to avoid reliability issues. Previous aging analysis approaches often have a trade-off between accuracy and simulation time. In order to improve the efficiency of aging analysis while keeping high accuracy, this paper proposes an incremental simulation technique based on delta circuit models. Since aging process is often a gradual change, incremental simulation technique is very effective to reduce the simulation time of each iteration with almost the same accuracy. Furthermore, a dynamic aging sampling technique is also proposed to further improve the efficiency of aging analysis with little accuracy loss. As demonstrated in the experiments, the proposed approach is indeed an effective way to reduce the aging analysis time while keeping estimation accuracy. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ATS.2017.24 | 2017 IEEE 26th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
aging analysis,delta circuit,incremental simulation | Computer science,Circuit Failure,Electronic engineering,Design flow,Sampling (statistics),Circuit performance,MOSFET,Circuit models,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5386-3516-2 | 0 |
PageRank | References | Authors |
0.34 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Si-Rong He | 1 | 1 | 0.70 |
| Nguyen Cao Qui | 2 | 1 | 0.70 |
| Yu-Hsuan Kuo | 3 | 0 | 0.34 |
| Chien-Nan Jimmy Liu | 4 | 97 | 27.07 |