Paper Info
Title
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS
Abstract
To eliminate the worst-case timing margins, a 13-transistor holosymmetrical transition detector (HTD) is proposed for use in timing variation resilient systems. The HTD achieves low overhead and wide-voltage-range operation via monitoring the discharge at the floating node of two-stage CMOS inverters. Using local detection and global clock stalling, the system is stalled immediately for one cycle when an error occurs, allowing the variation resilient technique to be integrated into any circuits without architectural changes. Plus, there is no need of an error recovery mechanism by keeping the system working at the point before the first failure (PBFF) and utilizing the time-borrowing characteristics of the latch. Applied on an 8th-order filter test chip in 40nm CMOS process, without changing the system architecture, chip's measurement results demonstrate that it improves energy efficiency by 45.6%/28.1% and throughput by 179.31%/28.2% in near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (0.474V) /super-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (1.1V) while incurring a 4.37% area overhead compared to a baseline design.
Year
DOI
Venue
2017
10.1109/ASSCC.2017.8240253
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
Field
DocType
transition detector,wide-voltage-range,in-situ timing monitoring,resilient design,time borrowing
Computer science,Efficient energy use,Voltage,Electronic engineering,Chip,CMOS,Systems architecture,Throughput,Electronic circuit,Detector
Conference
ISBN
Citations 
PageRank 
978-1-5386-3179-9
1
0.36
References 
Authors
8
4
Name
Order
Citations
PageRank
Wentao Dai112.05
Weiwei Shan22212.51
Xinning Liu384.02
Jun Yang458839.42