Name
Abstract | ||
|---|---|---|
In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics. Our method is based on connecting a time-to-digital converter to the output of the flip flop under test, rather than using a phase shifted clock, as conventionally done. We present the details of an FPGA implementation of our approach and show its feasibility through an experimental evaluation, whose results favorably match those obtained by the conventional method. The benefits of the novel scheme are the ability to perform a calibration for the delay steps, a speed-up of the measurement process, and the availability of a more comprehensive and ordered measurement data set. Especially the latter can be of crucial importance when (even multiple) glitches or oscillation are suspected to result from metastability, or when the temporal distribution of upsets matters (bursts of upsets, e.g.). |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1016/j.microrel.2017.11.017 | Microelectronics Reliability |
Keywords | Field | DocType |
Metastability,Time-to-digital converter,TDC,Late transition detection,Carry chain | Glitch,Oscillation,Field-programmable gate array,Electronic engineering,Upset,Metastability,Engineering,Flip-flop,Time-to-digital converter,Multi-core processor | Journal |
Volume | ISSN | Citations |
80 | 0026-2714 | 1 |
PageRank | References | Authors |
0.39 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Polzer | 1 | 49 | 8.43 |
| Florian Huemer | 2 | 3 | 2.46 |
| Andreas Steininger | 3 | 308 | 49.17 |