Paper Info
Title
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA.
Abstract
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities. While leading companies successfully advance their HESoC products, research lags behind due to the challenges of building a prototyping platform that unites an industry-standard host processor with an open research PMCA architecture. In this work we introduce HERO, an FPGA-based research platform that combines a PMCA composed of clusters of RISC-V cores, implemented as soft cores on an FPGA fabric, with a hard ARM Cortex-A multicore host processor. The PMCA architecture mapped on the FPGA is silicon-proven, scalable, configurable, and fully modifiable. HERO includes a complete software stack that consists of a heterogeneous cross-compilation toolchain with support for OpenMP accelerator programming, a Linux driver, and runtime libraries for both host and PMCA. HERO is designed to facilitate rapid exploration on all software and hardware layers: run-time behavior can be accurately analyzed by tracing events, and modifications can be validated through fully automated hard ware and software builds and executed tests. We demonstrate the usefulness of HERO by means of case studies from our research.
Year
DOI
Venue
2017
10.3929/ethz-b-000219249
arXiv: Hardware Architecture
Field
DocType
Volume
RISC-V,HERO,Computer science,Parallel computing,Field-programmable gate array,Software,Multi-core processor,Toolchain,Tracing,Scalability,Embedded system
Journal
abs/1712.06497
Citations 
PageRank 
References 
1
0.90
18
Authors
5
Name
Order
Citations
PageRank
Andreas Kurth111.24
Pirmin Vogel2194.69
Alessandro Capotondi3398.25
Andrea Marongiu433739.19
Luca Benini5131161188.49