| HePREM: A Predictable Execution Model for GPU-based Heterogeneous SoCs | 0 | 0.34 | 2021 |
| A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment | 0 | 0.34 | 2021 |
| A Synergistic Approach to Predictable Compilation and Scheduling on Commodity Multi-Cores | 0 | 0.34 | 2020 |
| Mixed-data-model heterogeneous compilation and OpenMP offloading | 0 | 0.34 | 2020 |
| Evaluating Controlled Memory Request Injection to Counter PREM Memory Underutilization. | 0 | 0.34 | 2020 |
| FlexFloat: A Software Library for Transprecision Computing | 3 | 0.42 | 2020 |
| Dissecting the CUDA scheduling hierarchy: a Performance and Predictability Perspective | 1 | 0.35 | 2020 |
| Combining PREM Compilation and Static Scheduling for High-Performance and Predictable MPSoC Execution | 0 | 0.34 | 2019 |
| Extending the Lifetime of Nano-Blimps via Dynamic Motor Control | 3 | 0.66 | 2019 |
| Taming Data Caches For Predictable Execution On Gpu-Based Socs | 0 | 0.34 | 2019 |
| Exploring Shared Virtual Memory for FPGA Accelerators with a Configurable IOMMU | 0 | 0.34 | 2019 |
| Design And Evaluation Of Smallfloat Simd Extensions To The Risc-V Isa | 0 | 0.34 | 2019 |
| The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores. | 1 | 0.35 | 2018 |
| Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. | 0 | 0.34 | 2018 |
| On the Cost of Freedom From Interference in Heterogeneous SoCs. | 0 | 0.34 | 2018 |
| Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution. | 3 | 0.38 | 2018 |
| Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. | 1 | 0.35 | 2018 |
| Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based. | 0 | 0.34 | 2018 |
| HePREM: Enabling predictable GPU execution on heterogeneous SoC | 2 | 0.41 | 2018 |
| Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators. | 1 | 0.38 | 2018 |
| Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine | 0 | 0.34 | 2018 |
| Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators. | 2 | 0.38 | 2018 |
| A Transprecision Floating-Point Platform For Ultra-Low Power Computing | 1 | 0.35 | 2018 |
| HERO: an open-source research platform for HW/SW exploration of heterogeneous manycore systems | 0 | 0.34 | 2018 |
| Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law. | 3 | 0.38 | 2018 |
| Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking. | 3 | 0.41 | 2018 |
| Enabling zero-copy OpenMP offloading on the PULP many-core accelerator | 1 | 0.38 | 2017 |
| Lightweight Virtual Memory Support for Zero-Copy Sharing of Pointer-Rich Data Structures in Heterogeneous Embedded SoCs. | 4 | 0.46 | 2017 |
| Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. | 13 | 0.59 | 2017 |
| On the Accuracy of Near-Optimal CPU-Based Path Planning for UAVs. | 0 | 0.34 | 2017 |
| Efficient Virtual Memory Sharing via On-Accelerator Page Table Walking in Heterogeneous Embedded SoCs. | 2 | 0.40 | 2017 |
| Ultra low-power visual odometry for nano-scale unmanned aerial vehicles. | 4 | 0.43 | 2017 |
| GPUguard: Towards supporting a predictable execution model for heterogeneous SoC. | 7 | 0.57 | 2017 |
| HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA. | 1 | 0.90 | 2017 |
| Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support. | 2 | 0.40 | 2016 |
| VirtualSoC: A Research Tool for Modern MPSoCs. | 3 | 0.41 | 2016 |
| Always-on motion detection with application-level error control on a near-threshold approximate computing platform. | 0 | 0.34 | 2016 |
| Exploring Single Source Shortest Path Parallelization on Shared Memory Accelerators. | 0 | 0.34 | 2016 |
| An Optimized Task-Based Runtime System For Resource-Constrained Parallel Accelerators | 0 | 0.34 | 2016 |
| Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. | 1 | 0.39 | 2016 |
| Enabling The Heterogeneous Accelerator Model On Ultra-Low Power Microcontroller Platforms | 3 | 0.38 | 2016 |
| Enabling OpenVX support in mW-scale parallel accelerators. | 1 | 0.36 | 2016 |
| He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores. | 1 | 0.35 | 2016 |
| An energy-efficient parallel algorithm for real-time near-optimal UAV path planning. | 4 | 0.50 | 2016 |
| Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators | 1 | 0.35 | 2015 |
| OpenMP and timing predictability: a possible union? | 14 | 0.62 | 2015 |
| A framework for optimizing OpenVX applications performance on embedded manycore accelerators | 1 | 0.35 | 2015 |
| Synergistic Architecture and Programming Model Support for Approximate Micropower Computing | 0 | 0.34 | 2015 |
| Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-cores | 0 | 0.34 | 2015 |
| Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters | 5 | 0.38 | 2015 |
