A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. - Citegraph

Paper Info

Title
A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology.

Abstract
This paper presents a six-transistor bitcell SRAM with pMOS access transistor. Utilizing pMOS access transistor results in lower zero-level degradation (ZLD) and, hence, higher read stability. In addition, the access transistor connected to the internal node holding VDD acts as a stabilizer and counter balances the effect of ZLD. In order to improve the writability, wordline (WL) boosting is explo...

Year	DOI	Venue
2018	10.1109/JSSC.2017.2747151	IEEE Journal of Solid-State Circuits
Keywords	Field	DocType
Random access memory,Circuit stability,Boosting,MOSFET,Sensors,Stability analysis	NMOS logic,Computer science,Chip,Electronic engineering,Static random-access memory,CMOS,Transistor,PMOS logic,MOSFET,Energy consumption,Electrical engineering	Journal
Volume	Issue	ISSN
53	2	0018-9200
Citations	PageRank	References
2	0.37	0
Authors
2

Authors (2 rows)

Cited by (2 rows)

References (0 rows)

Name	Order	Citations	PageRank
Morteza Nabavi	1	2	0.37
Manoj Sachdev	2	669	88.45

1