Paper Info
Title
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs
Abstract
Scan based error detection architectures for hybrid, carry-free radix-2 and radix-4 addition operations using redundant arithmetic are presented in this paper. Such addition operations have been chosen as representative examples as they are free from carry propagation delay and are ideal from the viewpoint of technology mapping of the logic elements onto the FPGA slices. The architectures have been conceived following the design paradigm of target FPGA specific primitive instantiation coupled with location constraints, without any degradation in the speed of circuit operation as compared to the original circuit implementation without the scan operation. Our architectures also comfortably outperform the existing state-of-the-art error detection architectures in terms of speed and consumes less area.
Year
DOI
Venue
2017
10.1109/HiPC.2017.00021
2017 IEEE 24th International Conference on High Performance Computing (HiPC)
Keywords
Field
DocType
Redundant arithmetic,Error detection,Fault localization,Primitive Instantiation,Scan flip-flop,Adder,Carry chain,Look-Up Table,Field Programmable Gate Array
Lookup table,Design paradigm,Adder,Computer science,Field-programmable gate array,Scan chain,Arithmetic,Error detection and correction,Technology mapping,Carry propagation
Conference
ISSN
ISBN
Citations 
1094-7256
978-1-5386-2294-0
0
PageRank 
References 
Authors
0.34
11
2
Name
Order
Citations
PageRank
Ayan Palchaudhuri1117.67
Anindya Sundar Dhar29726.09