Name
Abstract | ||
|---|---|---|
Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.
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Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ASPDAC.2018.8297313 | ASP-DAC |
Keywords | Field | DocType |
DRAM, built-in self-test, channel-based DRAM, test, March test | Dram,Latency (engineering),Computer science,Communication channel,Multi channel,Electronic engineering,Control system,Computer hardware,Built-in self-test,Random access,High bandwidth | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4503-6007-4 | 0 |
PageRank | References | Authors |
0.34 | 10 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuan-Te Wu | 1 | 4 | 1.11 |
| Jin-Fu Li | 2 | 662 | 59.17 |
| chihyen lo | 3 | 57 | 8.68 |
| Jenn-Shiang Lai | 4 | 3 | 1.78 |
| Ding-Ming Kwai | 5 | 521 | 46.85 |
| Yung-Fa Chou | 6 | 244 | 23.76 |